訊號正負緣偵測

正負緣偵測主要是訊透過D Flip Flop產生一個clock時間的差異後再處理,一般會有二種寫法來實現。

(1) 把其中一個訊號反相再AND處理即可產生正/負緣訊號。

assign POS_signal_o0 = ~signal_i_q1 & signal_i_q0;
assign NEG_signel_o0 = signal_i_q1 & ~signal_i_q0;

(2) 經由判斷式的方法來產生正/負緣訊。
assign POS_signal_o1 = ({signal_i_q1,signal_i_q0} == 2'b01) ? 1'b1 : 1'b0;
assign NEG_signel_o1 = ({signal_i_q1,signal_i_q0} == 2'b10) ? 1'b1 : 1'b0;

RTL 如下:

`timescale 1ns/100ps  
////// … . .. –.. .   – …. .   — — — . -. – ////// 									  																								  																			
// Author              : TienYao			  																
// Source Code Name	   : POSandNEGdetection.v					  																				
// Function Description: Positive edge and negative edge detection    														 
// ===========================================================
module POSandNEGdetection
(
	input clk,
	input rst_n,
	input signal_i,
	output POS_signal_o0,
	output NEG_signel_o0,
	output POS_signal_o1,
	output NEG_signel_o1
);


reg signal_i_q0;
reg signal_i_q1;
always @(posedge clk or negedge rst_n)
begin
	if(!rst_n)
	begin
		{signal_i_q1,signal_i_q0} <= 2'b00;
	end
	else
	begin
		signal_i_q0 <= signal_i;
		signal_i_q1 <= signal_i_q0;
	end
end

assign POS_signal_o0 = ~signal_i_q1 & signal_i_q0;
assign NEG_signel_o0 =  signal_i_q1 & ~signal_i_q0;

assign POS_signal_o1 = ({signal_i_q1,signal_i_q0} == 2'b01) ? 1'b1 : 1'b0;
assign NEG_signel_o1 = ({signal_i_q1,signal_i_q0} == 2'b10) ? 1'b1 : 1'b0;

endmodule

Testbench 如下:

`timescale 1ns/100ps  
////// … . .. –.. .   – …. .   — — — . -. – ////// 									  																								  																			
// Author              : TienYao			  																
// Source Code Name	   : POSandNEGdetection_tb.v					  																				
// Function Description: Testbench for POSandNEGdetection.v    														 
// ===========================================================
module POSandNEGdetection_tb;

reg  clk;
reg  rst_n;
reg  signal_i;
wire POS_signal_o0;
wire NEG_signel_o0;
wire POS_signal_o1;
wire NEG_signel_o1;
 
POSandNEGdetection DUT
(
	.clk			(clk		  ),
	.rst_n			(rst_n		  ),
	.signal_i     	(signal_i     ),
	.POS_signal_o0 	(POS_signal_o0),
	.NEG_signel_o0 	(NEG_signel_o0),
	.POS_signal_o1	(POS_signal_o1),
	.NEG_signel_o1	(NEG_signel_o1)
);


initial
begin
	clk = 0;
	rst_n = 0;
	signal_i = 0;
end

always #10 clk = ~clk;

task rstini;
begin
	repeat(10) @(posedge clk);
	rst_n = 1;
end
endtask

initial
begin
	rstini;
	#100;
	signal_i = 1;
	#200;
	signal_i = 0;
	#100;
	$stop;
end

endmodule

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